Study of Ultra-low Specific On-resistance and High Breakdown Voltage SOI LDMOS based on Electron Accumulation Effect

Abstract A novel stepped L-shaped trench gate silicon-on-insulator (SOI) lateral double-diffused metal oxide semiconductor field-effect transistor (LDMOS) with N-pillar (SLTGN-LDMOS) is proposed. SLTGN-LDMOS contains a highly doped N-pillar, assisting in reducing the specific on-resistance (Ron,sp). The (SLTG) attracts electrons to attach edge of trench, thus directing more current flow along edge, which decreases Ron,sp effectively. Furthermore, new electric field peaks are generated on surface drift region, increasing breakdown voltage (BV). As result, compared conventional structure (C-LDMOS), BV increases from 63 V 162.7 V, and 1.85 mΩ·cm2 1.46 mΩ·cm2. Then, figure merit (FOM1, BV2 / Ron.sp) remarkably 2.15 MW/cm2 18.13 MW/cm2. In addition, maximum temperature 395.3 K, slightly lower than 398.7 K C-LDMOS.